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KAUST Research Conference - PCCFD
22 to 24 May - 2017
Professor of EECS, UC Berkeley
Professor Phillip Colella received his A.B. (1974), M.A. (1976) and Ph.D. (1979) degrees from the University of California at Berkeley, all in applied mathematics. He has been a staff scientist at the Lawrence Berkeley National Laboratory and at the Lawrence Livermore National Laboratory, and a Professor in the Mechanical Engineering Department at the University of California at Berkeley. He is currently a Senior Scientist for the Applied Numerical Algorithms Group in the Computational Research Division at the Lawrence Berkeley National Laboratory, and a Professor in Residence in the Electrical Engineering and Computer Science Department at UC Berkeley. He has developed high-resolution and adaptive numerical algorithms for partial differential equations and numerical simulation capabilities for a variety of applications in science and engineering. He has also participated in the design of high-performance software infrastructure for scientific computing, including software libraries, frameworks, and programming languages.
Honors and awards include the IEEE Sidney Fernbach Award for high-performance computing in 1998, the SIAM/ACM prize (with John Bell) for computational science and engineering in 2003, election to the US National Academy of Sciences in 2004, and election to the inaugural class of SIAM Fellows in 2009.
All sessions by Phillip Colella
Design of Numerical Algorithms for Partial Differential Equations on Next-Generation Computer Architectures
The end of Dennard scaling, resulting in the use of low-power processor technologies in HPC, is leading to the deployment of large-scale parallelism on a single compute node to obtain high performance. By 2024, the cost of flops on HPC-capable systems, in terms of dollars and power, is expected to decrease by a factor of 100, relative to what it was in 2014. However, the performance of memory systems for these processors will not keep pace, due to power constraints. The ratio of the peak aggregate flop rate to the bandwidth between DRAM and the floating point units, as well as ratio of flop rate to overall size of DRAM, will be significantly less than what we have been used to for the last 20 years. Traditional numerical methods for partial differential equations have low arithmetic intensity (AI). Such methods can only obtain a small fraction of peak performance on such systems: performance is limited by rate at which data can get to the floating point units. In this talk, we will give several examples of how these new architectures lead to new tradeoffs in the design of numerical algorithms for PDE, trading flops for bytes in a way that reduces the overall data traffic and memory footprint required to obtain a given level of accuracy in a calculation. We will focus our attention on structured-grid and particle methods; in those cases, the most obvious example of this approach is the use of methods that are higher-order accurate than the ones customarily used (mostly second order) in multi-physics calculations. High-order methods can, in principle, obtain a given level of accuracy for fewer degrees of freedom, and the arithmetic intensity increases with the order of accuracy of the method. The design of new discretization methods is central to the success of this endeavor. However, there are other issues that need to be addressed in order for this approach to be successful. The design of high-order accurate methods that will retain their apparent advantages for realistic applications is nontrivial, and significant effort is required to realize the theoretically predicted performance by careful implementation.
Professor of EECS, UC Berkeley
09:00 - 09:55